VME-1064 PLC module DCS system module

The design of the Relay Output Board, as shown in the functional block diagram in Figure 3.1-1, consists primarily of four sections which are: a. VMEbus foundation logic. b. Device addressing. c. Output registers and relay drivers. d. 32 one Form A relays. To perform data transfers, data is written to the Output Data Registers. The appropriate outputs are selected via address bit A01, which selects one of the two banks of 16 bits for data outputs. The two data strobes, DSO and DS1, select word or byte access of the banks. The Data Transfer/Board Select Signal is logically gated with DSO and DS1 to produce active signals for data transfer. These gated signals activate output latches, which latch the output data for control of the relays. 3.2 DEVICE ADDRESSING The Relay Output Board is designed to support data transfers in supervisory or nonprivileged short I/O memory space. A jumper is provided, as shown in Figure 3.2-1 (Address Decode Block Diagram), to allow user selection of either I/O access. The jumper (J1) is factory configured (jumper J1 is not installed) to respond to short supervisory I/O access. As shown in Figure 3.2-1, 14 address select switches allow the user to establish a board base address any where in short I/O memory. 3.3 FOUNDATION LOGIC The VMEbus foundation logic for the Relay Output Board is shown in Figure 3.3-1. This logic consists primarily of data and address buffers and control signal buffers. The DTACK generator is factory preset for maximum data transfer. 3.4 OUTPUT REGISTERS AND RELAY DRIVERS A functional block diagram of the Output Registers and relay drivers is shown in Figure 3.4-1. Each register/driver function is designed using a 74LS273 8-bit register driving a Sprague:ULN2003A. This functional block diagram depicts the mapping of the 8-bit register outputs into the 7-bit relay driver I.C.s. CONTROL LOGIC V M E b 16 16-bit ADDRESSING 16 \/7 • DATA 16 TRANSCEIVERS 8- or 16-bit DATA TRANSFERS Mercury wetted or dry reed. Figure 3.1 im. ADDRESS COMPARE 2 r OUTPUT CONTROL R O E U G T i P S U T T E R S 32 —71-0".. R E L A Y D R V E R S 1. Functional Block Diagram ADDRESS SWITCHES 1 FORM A RELAYS* M2200/F3.1 -1 2/____0....2 000-ZZ00-9 • • 500-002200-000 C AMO to AM5 ri• 0 JUMPER SELECTABLE M (NONPRIVILEGED OR LWORD* P SUPERVISORY SHORT I/O) A R ACK* A T 0 R = V M E C b u S A8 to A15 0 M P A R A T S W L I 0 T G C I H C E 0 S R = C 0 S M W A2 to A7 P I A T R A C I H T E 0 S R = • • P1 (DATA TRANSFER) BOARD SELECT 411 M2200/F3.2-1 Figure 3.2-1. Address Decode Block Diagram 3-3 500-002200-000 P1 V M E b S A15 to A01 AM5 to AMO 16 BOARD ADDRESS AND ADDRESS MODIFIER COMPARATOR D15 to DO 5 / DATA TRANSCEIVERS CONTROL RECEIVER CLK DTACK* 1 DTACK GENERATOR Figure 3.3-1 VMEbus Interface Logic and Interface Signals M2200/F3.3-1 3-4 500-002200-000 EN D E 1Y1 WRITE R1L GDSODH C 0 1Y2 WRITE ROL GDS1 DL E 2Y1 WRITE R1 U R A01 2Y2 WRITE ROU • IDB08 to 15 ROU 74LS273 WRITE ROU 4 IDB00 to 07 ROL 74LS273 , 4 ULN2003A ODB28 to 31 OD24 to 31 ULN2003A ODB21 to 27 WRITE ROL 4 IDB08 to 15 R1U 74LS273 OD16 to 23 ULN2003A WRITE R1U IDB00 to 07 R1L 74LS273 ODO8 t 15 --111111 WRITE R1L BOARD SELECT WRITE ODOO to 07 ULN2003A ULN2003A ODB14 to 20 ODB07 to 13 ODBOO to 06 M2200/F3.4-1 Figure 3.4-1. Output Registers and Driver Functional Block Diagram 3-5 500-002200-000 3.5 OUTPUT RELAY A typical output relay is shown in Figure 3.5-1. Optional contact protection electronics is shown. Each of the 32 relays is driven from the output logic shown in Figure 3.4-1. The relay contacts are routed to two front panel DIN connectors whose pin assig